Design of Mathematical Coprocessor of Simple Precision using Spartan 3E

**Authors:
**
J. Antonio Álvarez, Michael Lindig B.

Polibits, 38, pp. 81-90, 2008.

**
Abstract: **
Floating Point Unit (FPU) is also known as mathematical coprocessor and is a specialized component of the CPU dedicated to floating point operations. Basic operations of any FPU are arithmetic (sum and multiplication), though some more complex systems are also able to perform trigonometric or exponential calculations. Not all CPUs have an additional FPU.
If there is no FPU present, then CPU can use some programs written in microcode for emulation of floating point operations using arithmetic-logical unit (ALU). This reduces the cost of
the hardware but slow down the processing speed. The purpose of this paper is to propose an implementation of the mathematical coprocessor using VHDL, for its further implementation in FPGA.

**
Keywords: **
FPU; mathematical coprocessor; VHDL; FPGA

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Design of Mathematical Coprocessor of Simple Precision using Spartan 3E,
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